UPS 250, UPS 300, UPS 500, UPS 600, UPS 750 and UPS 900 Uninterruptible Power Supply Caterpillar


Device Bus Network

Usage:

UPS 250 APZ

MODBUS Register Map

  • The UPS Series 300 supports the following protocols: MODBUS/TCP, Class 0 and MODBUS/RTU.

  • All registers are read only. The registers are accessed with MODBUS FC3. MODBUS FC3 allows multiple registers to be read.

  • There are 5 register groups: System, MMU, Event, Status and Summary.

  • Register pairs, shown as (x)(x+1) represent a 32 bit floating point value. The lower numbered register contains bits 15 through 0 of the value. The higher numbered Register contains bits 31 through 16 of the floating point value.

  • Registers shown as (x) are 16 bit unsigned quantities.

  • References to a register number x is equivalent to MODBUS Register 40000+x.

System Group

The system group pertains to those signals that are common to all of the MMUs that are in a system.

Table 1
System Registers    
Register     Group     Description     Units    
(1)     System     Firmware Revision, Lower     Refer to "Note 1".    
(2)     System     Firmware Revision, Upper        
(3)     System     FPGA Revision, Lower     Refer to "Note 2".    
(4)     System     FPGA Revision, Upper        
(5)     System     Notice Active     0 or 1    
(6)     System     Alarm Active     0 or 1    
(7)     System     System Mode     (integer)    
(8)     System     System State     (integer)    
(9)     System     System Year     4 digit year    
(10)     System     System Month     1 to 12    
(11)     System     System Date     1 to 31    
(12)     System     System Hour     0 to 23    
(13)     System     System Minute     0 to 59    
(14)     System     System Second     0 to 59    
(15)(16)     System     Output Frequency     Hertz    
(17)(18)     System     Input Frequency     Hertz    
(19)(20)     System     Output Power Factor     0.0 to 1.0    
(21)(22)     System     Input Power Factor     0.0 to 1.0    
(23)(24)     System     Percent Energy     Percent    
(25)(26)     System     Percent Load     Percent    
(27)(28)     System     Output Power     Kilowatts    
(29)(30)     System     Output KVA     KVA    
(31)(32)     System     Input Power     Kilowatts    
(33)(34)     System     Input KVA     KVA    
(35)(36)     System     Input Line Volt AB     Vac    
(37)(38)     System     Input Line Volt BC     Vac    
(39)(40)     System     Input Line Volt CA     Vac    
(41)(42)     System     Bypass Line Volt AB     Vac    
(43)(44)     System     Bypass Line Volt BC     Vac    
(45)(46)     System     Bypass Line Volt CA     Vac    
(47)(48)     System     Output Line Volt AB     Vac    
(49)(50)     System     Output Line Volt BA     Vac    
(51)(52)     System     Output Line Volt CA     Vac    
(53)(54)     System     Input Current Phase A     Amps    
(55)(56)     System     Input Current Phase B     Amps    
(57)(58)     System     Input Current Phase C     Amps    
(59)(60)     System     Output Current Phase A     Amps    
(61)(62)     System     Output Current Phase B     Amps    
(63)(64)     System     Output Current Phase C     Amps    

Note 1

Firmware Revisions are shown as: M.mmXY (example: 1.02)

Where:

  • M represents the major revision, mm represents the minor revision, X represents the Beta letter and Y represents the Developer Letter. For production code, the Beta and developer letters will be null.

  • The Lower 16 bits of the Firmware Revision contain the Beta Letter (upper byte) and Developer Letter (lower byte).

  • The Upper 16 bits contain the Major Revision (upper byte) and the Minor Revision (lower byte).

For example, if Register 1 contains 0x7068, and Register 2 contains 0x005a, The firmware revision would be shown as 0.90ph, indicating major/minor revision level of .90, beta version p, developer h.

Note 2

The FPGA revision is shown as X.YZ, where X and Y are numeric and represent the major revisions and the minor revsions. Z is a Beta letter. Example (1.30)

The FPGA revision information can be decoded as follows:

  • Major.Minor = (float)Register 3 / 100

  • The Beta letter is ASC((Register 4 & 255) + 0x60)

  • The Product Family code is contained in the upper 8 bits of Register 4. The product code will always be 0 (zero) for the UPS Series 300. For example, if register 3 contains 0x00A0 and Register 4 contains 0x0008, the FPGA revision would be shown as 1.6h and would indicate a valid Series 300 UPS FPGA.

MMU Detail Group

Table 2
Detail Registers    
Register     Group     Description     Units    
(100)(101)     MMU detail     Input Volts AB     VAC    
(102)(103)     MMU detail     Input Volts BC     VAC    
(104)(105)     MMU detail     Input Volts CA     VAC    
(106)(107)     MMU detail     Filter Volts AB     VAC    
(108)(109)     MMU detail     Filter Volts BC     VAC    
(110)(111)     MMU detail     Filter Volts CA     VAC    
(112)(113)     MMU detail     Output Volts AB     VAC    
(114)(115)     MMU detail     Output Volts BC     VAC    
(116)(117)     MMU detail     Output Volts CA     VAC    
(118)(119)     MMU detail     Inverter Current A     Amps    
(120)(121)     MMU detail     Inverter Current B     Amps    
(122)(123)     MMU detail     Inverter Current C     Amps    
(124)(125)     MMU detail     Input Current A     Amps    
(126)(127)     MMU detail     Input Current B     Amps    
(128)(129)     MMU detail     Input Current C     Amps    
(130)(131)     MMU detail     Output Current A     Amps    
(132)(133)     MMU detail     Output Current B     Amps    
(134)(135)     MMU detail     Output Current C     Amps    
(136)(137)     MMU detail     Target Output Volts AB     VAC    
(138)(139)     MMU detail     Target Output Volts BC     VAC    
(140)(141)     MMU detail     Target Output Volts CA     VAC    
(142)(143)     MMU detail     DC Offset Correction AB     VAC    
(144)(145)     MMU detail     DC Offset Correction BC     VAC    
(146)(147)     MMU detail     DC Offset Correction CA     VAC    
(148)(149)     MMU detail     Output Voltage Setpoint AB     VAC    
(150)(151)     MMU detail     Output Voltage Setpoint BC     VAC    
(152)(153)     MMU detail     Output Voltage Setpoint CA     VAC    
(154)(155)     MMU detail     Input Volts AN     VAC    
(156)(157)     MMU detail     Input Volts BN     VAC    
(158)(159)     MMU detail     Input Volts CN     VAC    
(160)(161)     MMU detail     Output Frequency     Hertz    
(162)(163)     MMU detail     Output MMU Power     KW    
(164)(165)     MMU detail     Output MMU KVA     KVA    
(166)(167)     MMU detail     Output Power Factor     0.0 to 1.0    
(168)(169)     MMU detail     Input Frequency     Hertz    
(170)(171)     MMU detail     Input MMU Power     KW    
(172)(173)     MMU detail     Input MMU KVA     KVA    
(174)(175)     MMU detail     Input Power Factor     0.0 to 1.0    
(176)(177)     MMU detail     Cabinet Temperature     °C    
(178)(179)     MMU detail     Air Inlet
Temperature    
°C    
(180)(181)     MMU detail     Static Switch
Temperature    
°C    
(182)(183)     MMU detail     Genset Start
IGBT
Temperature    
°C    
(184)(185)     MMU detail     Positive DC Bus Voltage     VDC    
(186)(187)     MMU detail     Negative DC Bus Voltage     VDC    
(188)(189)     MMU detail     Tachometer     RPM    
(190)(191)     MMU detail     Percent Energy     %    
(192)(193)     MMU detail     Vacuum Gauge     milliTorr    
(194)(195)     MMU detail     Top Field Coil Current     Amps    
(196)(197)     MMU detail     Bottom Field Coil Current     Amps    
(198)(199)     MMU detail     Bottom Bearing Force     Pounds    
(200)(201)     MMU detail     Lateral Vibration     Gs    
(202)(203)     MMU detail     Axial Vibration     Gs    
(204)(205)     MMU detail     Top Field Coil
Temperature    
°C    
(206)(207)     MMU detail     Bottom Field Coil
Temperature    
°C    
(208)(209)     MMU detail     Armature
Temperature    
°C    
(210)(211)     MMU detail     Top Field Coil IGBT
Temperature    
°C    
(212)(213)     MMU detail     Bottom Field Coil IGBT
Temperature    
°C    
(214)(215)     MMU detail     Top Bearing
Temperature    
°C    
(216)(217)     MMU detail     Bottom Bearing
Temperature    
°C    
(218)(219)     MMU detail     RPS Advance setpoint     0 to 255    
(220)     MMU detail     MMU Mode     Integer    
(221)     MMU detail     MMU State     Integer    

Event Log Group

The Event Log Group provides a way to read the event log from the UPS Series 300. Events are stored in the internal memory of the UPS according to severity.

  • Status Events are normal occurring events that are deemed important enough to store in the event memory, but are not associated with an error condition.

  • Notice Events indicate a possible failure or an abnormal condition and should be investigated.

  • Alarm Events require immediate attention.

The Message itself is sent as ASCII text in registers 256 through 296 and can be up to 80 characters in length, plus a trailing null. For messages that are less than 80 characters long, the trailing bytes are zeroed. Attempts to read a message index that is greater than the number of indicated messages (in registers 250, 251 or 252) will result in a null string (all message bytes being zeroed).

Refer to the following steps in order to retrieve the event log:

  1. Read the number of "All" messages, "Alarm" messages and/or "Warning" messages.

    Refer to the following Registers: 250, 251 and 252.

  1. If there are more than 0 messages, set the Command register for the desired message level.

    A reset command should be issued first. Subsequent Advance commands should be issued to progress through all the events.

    If another message is available, the ASCII string area will contain the ASCII characters for the message. The end of the message will be padded with NULL characters. If no other messages are available, the ASCII string area will contain zeros.

Pseudo-coded routines for reading the entire event log, and for periodically checking for new event messages, are shown below. Refer to Illustration 1.

Refer to Table 3 for the Commands for the following Registers: 253, 254 and 255.

Table 3
Command Values    
Value     Meaning     Description    
0     Reset     Sets the internal index to the oldest message stored in the event log.This command should be issued at least once when reading the event log.    
1     Advance     Advances the internal index to the next message of the appropriate event type. If there are no more messages of the appropriate type available, a NULL string will be placed in the ASCII string registers.    



Illustration 1g01084074

Pseudo-coded routine

Note: The UPS Series 300 accumulates events in 2 sectors in flash memory. Each sector can hold 2038 events. When a sector is filled (number of all events = 2038), the most-recent 1440 events are copied to the other (erased) sector before adding new messages to the event log. Therefore, it is possible for the values in registers 250, 251 and/or 252 to suddenly decrease. This must be taken into account when designing code which examines these registers.

Table 4
Event Registers    
Register     Group     Read_Write     Description    
(250)     Event     R     Number of All Messages    
(251)     Event     R     Number of Warning and Alarm Messages    
(252)     Event     R     Number of Alarm Messages Only    
(253)     Event     R/W     "All Messages" Command Register    
(254)     Event     R/W     "Warning and Alarm Messages" Command Register    
(255)     Event     R/W     "Alarm Messages Only" Command Register    
(256)     Event     R     Bytes 0 and 1 of the ASCII message string    
(257)     Event     R     Bytes 2 and 3 of the ASCII message string    
(258)     Event     R     Bytes 4 and 5 of the ASCII message string    
(259)     Event     R     Bytes 6 and 7 of the ASCII message string    
(260)     Event     R     Bytes 8 and 9 of the ASCII message string    
(261)     Event     R     Bytes 10 and 11 of the ASCII message string    
(262)     Event     R     Bytes 12 and 13 of the ASCII message string    
(263)     Event     R     Bytes 14 and 15 of the ASCII message string    
(264)     Event     R     Bytes 16 and 17 of the ASCII message string    
(265)     Event     R     Bytes 18 and 19 of the ASCII message string    
(266)     Event     R     Bytes 20 and 21 of the ASCII message string    
(267)     Event     R     Bytes 22 and 23 of the ASCII message string    
(268)     Event     R     Bytes 24 and 25 of the ASCII message string    
(269)     Event     R     Bytes 26 and 27 of the ASCII message string    
(270)     Event     R     Bytes 28 and 29 of the ASCII message string    
(271)     Event     R     Bytes 30 and 31 of the ASCII message string    
(272)     Event     R     Bytes 32 and 33 of the ASCII message string    
(273)     Event     R     Bytes 34 and 35 of the ASCII message string    
(274)     Event     R     Bytes 36 and 37 of the ASCII message string    
(275)     Event     R     Bytes 38 and 39 of the ASCII message string    
(276)     Event     R     Bytes 40 and 41 of the ASCII message string    
(277)     Event     R     Bytes 42 and 43 of the ASCII message string    
(278)     Event     R     Bytes 44 and 45 of the ASCII message string    
(279)     Event     R     Bytes 46 and 47 of the ASCII message string    
(280)     Event     R     Bytes 48 and 49 of the ASCII message string    
(281)     Event     R     Bytes 50 and 51 of the ASCII message string    
(282)     Event     R     Bytes 52 and 53 of the ASCII message string    
(283)     Event     R     Bytes 54 and 55 of the ASCII message string    
(284)     Event     R     Bytes 56 and 57 of the ASCII message string    
(285)     Event     R     Bytes 58 and 59 of the ASCII message string    
(286)     Event     R     Bytes 60 and 61 of the ASCII message string    
(287)     Event     R     Bytes 62 and 63 of the ASCII message string    
(288)     Event     R     Bytes 64 and 65 of the ASCII message string    
(289)     Event     R     Bytes 66 and 67 of the ASCII message string    
(290)     Event     R     Bytes 68 and 69 of the ASCII message string    
(291)     Event     R     Bytes 70 and 71 of the ASCII message string    
(292)     Event     R     Bytes 72 and 73 of the ASCII message string    
(293)     Event     R     Bytes 74 and 75 of the ASCII message string    
(294)     Event     R     Bytes 76 and 77 of the ASCII message string    
(295)     Event     R     Bytes 78 and 79 of the ASCII message string    
(296)     Event     R     Bytes 80 and 81 of the ASCII message string    

Status Group

The Status Group are status registers for the system and MMU. Each bit has a particular meaning for a particular FPGA revision.

Table 5
System Status Registers    
Register     Group     Description    
(350)     Status     System Status Register 1    
(351)     Status     System Status Register 2    
(352)     Status     System Status Register 3    
(353)     Status     MMU Status Register A    
(354)     Status     MMU Status Register B    
(355)     Status     MMU Status Register C    
(356)     Status     MMU Status Register D    
(357)     Status     MMU Status Register E    

Note: The three system status registers are only available on systems with a Systems Cabinet (in other words, systems that can support more than 1 MMU).

Table 6
Bit definitions for System Status Register 1    
Bit     Definition     Description    
15 (1)     SYS_CAB_USER_DATA_LOCK_BIT     communication with user interface board ok    
14     SYS_CAB_IO_DATA_LOCK_BIT     communication with i/o interface board ok    
13     SYS_CAB_FAN_DATA_LOCK_BIT     communication with fan interface board ok    
12     SYS_CAB_AC_DATA_LOCK_BIT     communication with AC interface board ok    
11     SYS_CAB_T3_FUSE_BIT     pwr supply xfrmr fuse okay    
10     SYS_CAB_T2_FUSE_BIT     pwr supply xfrmr fuse okay    
9     SYS_CAB_T1_FUSE_BIT     pwr supply xfrmr fuse okay    
8     SYS_CAB_SPARE_0     spare bit    
7     SYS_CAB_PS_2_OK_BIT     24 V power supply 2 okay    
6     SYS_CAB_PS_1_OK_BIT     24 V power supply 1 okay    
5     SYS_CAB_FAN_6_OK_BIT     spare bit    
4     SYS_CAB_FAN_5_OK_BIT     spare bit    
3     SYS_CAB_FAN_4_OK_BIT     spare bit    
2     SYS_CAB_FAN_3_OK_BIT     System cabinet fan 3 is okay    
1     SYS_CAB_FAN_2_OK_BIT     System cabinet fan 2 is okay    
0     SYS_CAB_FAN_1_OK_BIT     System cabinet fan 1 is okay    
( 1 ) Bit 15 is the most significant bit

Table 7
Bit definitions for System Status Register 2    
Bit     Definition     Description    
15     SYS_CAB_SS_FUSE_OK_BIT     Bypass Static Switch fuse is okay    
14     SYS_CAB_SPARE_BIT     spare bit    
13     SYS_CAB_SPARE_BIT     spare bit    
12     SYS_CAB_SPARE_BIT     spare bit    
11     SYS_CAB_SPARE_BIT     spare bit    
10     SYS_CAB_SPARE_BIT     spare bit    
9     SYS_CAB_SPARE_BIT     spare bit    
8     SYS_CAB_SPARE_8        
7     SYS_CAB_SPARE_7        
6     SYS_CAB_IN_6_CONTACT_BIT     System Cabinet remote input contact    
5     SYS_CAB_IN_5_CONTACT_BIT     System Cabinet remote input contact    
4     SYS_CAB_IN_4_CONTACT_BIT     System Cabinet remote input contact    
3     SYS_CAB_IN_3_CONTACT_BIT     System Cabinet remote input contact    
2     SYS_CAB_IN_2_CONTACT_BIT     System Cabinet remote input contact    
1     SYS_CAB_IN_1_CONTACT_BIT     System Cabinet remote input contact    
0     SYS_CAB_SPARE_BIT        

Table 8
Bit definitions for System Status Register 3    
Bit     Definition     Description    
15     SYS_CAB_BYPASS_ROTATION_CW     bypass input phase rotation is clockwise    
14     SYS_CAB_BYPASS_ROTATION_CCW     bypass input phase rotation is counter-clockwise    
13     SYS_CAB_FREQUENCY_LOCK        
12         Spare bits    
11         Spare bits    
10         Spare bits    
9         Spare bits    
8     SYS_CAB_K3_STATUS_ERR, K3     status bit does not match the "K3" command bit    
7     SYS_CAB_COMMUNICATION_ERR     error with one of the satellite sys. Cab. boards    
6     SYS_CAB_K3_CB_CURRENT_TRIP     bypass CB tripped because of current overload    
5     SYS_CAB_FAN_SPARE_5        
4     SYS_CAB_FAN_SPARE_4        
3     SYS_CAB_FAN_SPARE_3        
2     SYS_CAB_FAN_SPARE_2        
1     SYS_CAB_ZIGZAG_OL_RELAY_TRIP     zigzag xfrmr overload relay has tripped    
0     SYS_CAB_ZIGZAG_BREAKER_TRIP     zigzag breaker relay has tripped    

Table 9
Bit definitions for MMU Status Register A    
Bit     Definition     Description    
15     K3_STATUS_BIT     Bypass contactor status bit (1 = closed)    
14     K2_STATUS_BIT     MMU output contactor status bit (1 = closed)    
13     K1_STATUS_BIT     MMU input contactor status bit (1 = closed)    
12     USER_DATA_LOCK     MMU user interface board communications okay    
11     IO_DATA_LOCK     MMU input/ouput interface board communication okay    
10     FAN_DATA_LOCK     MMU fan interface board communications okay    
9     DC_DATA_LOCK     MMU DC interface board communications okay    
8     AC_DATA_LOCK     MMU AC interface board communications okay    
7     GS_DATA_LOCK (Optional)     MMU Genset Start interface board comm. okay    
6     UNLOADING_TO     Unloading controller had a timeout reaching setpoint    
5     LOW_SPEED_SHUTDOWN     Discharge ending because of flywheel speed    
4     FLY_MASTER_ENABLE     Flywheel Master Controller enabled    
3     EXT_SYNC_BIT     Synchronize output to external input source cmd bit    
2     K4_STATUS_BIT     Bypass static switch contactor status Bit    
1     S_BYP_SW_FUSE_OK_BIT     Bypass static switch fuse status bit    
0     MASTER_ENABLE     The MMU master controller is enabled    

Table 10
Bit definitions for MMU Status Register B    
Bit     Definition     Description    
13     DISCHARGING_BIT     MMU is discharging    
12     SPARE_BIT        
11     SPARE_BIT        
10     MMU_T2_FUSE_BIT     MMU power supply xfrmr 2 fuse okay    
9     MMU_T1_FUSE_BIT     MMU power supply xfrmr 1 fuse okay    
8     PS_3_BIT     MMU 24V DC power supply 3 okay    
7     PS_2_BIT     MMU 24V DC power supply 2 okay    
6     PS_1_BIT     MMU 24V DC power supply 1 okay    
5     FAN_5_BIT     MMU Fan 6 okay    
4     FAN_4_BIT     MMU Fan 5 okay    
3     FAN_3_BIT     MMU Fan 4 okay    
2     FAN_2_BIT     MMU Fan 3 okay    
1     FAN_1_BIT     MMU Fan 2 okay    
0     FAN_0_BIT     MMU Fan 1 okay    

Table 11
Bit definitions for MMU Status Register C    
Bit     Definition     Description    
14     AC_COUNTER_CLOCKWISE_BIT     MMU input has counter-clockwise phase rotation    
13     AC_CLOCKWISE_BIT     MMU input has clockwise phase rotation    
12     STATIC_SW_FULLY_ON_BIT     MMU Input static switch is turned on    
11     STATIC_SWITCH_TIMEOUT     Timeout controlling MMU input static switch    
10     OVERSPEED_ERR     Flywheel overspeed shutdown    
9     RPS_ERR     Rotor Position Sensor Error    
8     SKIIP_3_ERR     Flywheel SKIIP 3 error    
7     SKIIP_2_ERR     Flywheel SKIIP 2 error    
6     SKIIP_1_ERR     Flywheel SKIIP 1 error    
5     SKIIP_C_ERR     Utility Inverter Phase C SKIIP error    
4     SKIIP_B_ERR     Utility Inverter Phase B SKIIP error    
3     SKIIP_A_ERR     Utility Inverter Phase A SKIIP error    
2     FWI_DATALOCK_ERR_BIT     Flywheel Interface Board comm. error    
1     LOW_DC_BUS_ERR     A DC Bus had a low voltage error    
0     HI_DC_BUS_ERR     A DC Bus had a high voltage error    

Table 12
Bit definitions for MMU Status Register D    
Bit     Definition     Description    
15     BYPASS_AVAILABLE_BIT     Bypass input is qualified for bypass transfers    
14     EXT_SYNC_CMD_BIT     Discharge sync. to ext. downstream source    
13     BYPASS_SSW_OKAY_BIT     Bypass static switch is present and operating    
12     BYPASS_SYNC_BIT     Output is synchronized to the bypass source    
11     AHC_ENABLE_BIT     Active harmonic correction enable bit    
10     FLYWHEEL_SYS_ENABLE_BIT     The flywheel master controller enable bit    
9     REDUNDANT_MMU_BIT     The system has at least 1 MMU more than the load requires    
8     AVR_ENABLE_BIT     Automatic Voltage Regulation is enabled    
7     NEUTRAL_CONNECTED_BIT     System has a neutral connection    
6     K4_CONTROL_BIT     Bypass static switch contactor close cmd    
5     START_SWEEP_ENABLE_BIT     Rotor spin-up sweep is enabled    
4     K3_CONTROL_BIT     Bypass contactor open request    
3     K2_CONTROL_BIT     Output contactor close request    
2     K1_CONTROL_BIT     Input contactor close request    
1     UNLOADING_ENABLE_BIT     Rotor unloading controller is enabled    
0     STATIC_SWITCH_ENABLE_BIT     MMU input static switch is enabled    

Table 13
Bit definitions for MMU Status Register E    
Bit     Definition     Description    
15     DISCHARGE_ENABLE_BIT     MMU discharge is enabled    
14     FLYWHL_INV_ENABLE_BIT     MMU flywheel inverter is enabled    
13     FIELD_ENABLE_BIT     MMU field coil controller is enabled    
12     UTIL_INV_ENABLE_BIT     MMU Output Utility Inverter is enabled    
11     SYSTEM_ENABLE_BIT     MMU master controller enable command    
10     ALARM_ACTIVE     MMU has an active alarm event    
9     NOTICE_ACTIVE     MMU has an active notice event    

Summary Group

The summary group contains some information about each UPS Series 300 unit that is connected via the CAN bus. Register values for MMUs that are not present on the CAN bus are returned as zeros. There are registers for four UPS Series 300 units connected to each other via the CAN bus. Reading registers from a unit that is not connected to the bus will return zeros.

Table 14
Summary Registers    
Register     Group     Description    
(375)     Summary     Detected number of MMUs    
(376)     Summary     Expected number of MMUs    
(380)     Summary     MMU Mode, Unit 1    
(381)     Summary     MMU State, Unit 1    
(382)(383)     Summary     Tachometer, Unit 1    
(384)(385)     Summary     Percent Usable Energy, Unit 1    
(386)(387)     Summary     Cabinet Temperature, Unit 1    
(388)(389)     Summary     Vacuum Gauge, Unit 1    
(390)(391)     Summary     MMU Output Power, Unit 1    
(392)(393)     Summary     MMU Output KVA, Unit 1    
(394)(395)     Summary     MMU Input Power, Unit 1    
(396)(397)     Summary     MMU Input KVA, Unit 1    
(398)(399)     Summary     MMU Spare telemetry channel, Unit 1    
(400)(401)     Summary     MMU Spare telemetry channel, Unit 1    
(402)(403)     Summary     MMU Input Current Phase A, Unit 1    
(404)(405)     Summary     MMU Input Current Phase B, Unit 1    
(406)(407)     Summary     MMU Input Current Phase C, Unit 1    
(408)(409)     Summary     MMU Output Current Phase A, Unit 1    
(410)(411)     Summary     MMU Output Current Phase B, Unit 1    
(412)(413)     Summary     MMU Output Current Phase C, Unit 1    
(424)     Summary     MMU Mode, Unit 2    
(425)     Summary     MMU State, Unit 2    
(426)(427)     Summary     Tachometer, Unit 2    
(428)(429)     Summary     Percent Usable Energy, Unit 2    
(430)(431)     Summary     Cabinet Temperature, Unit 2    
(432)(433)     Summary     Vacuum Gauge, Unit 2    
(434)(435)     Summary     MMU Output Power, Unit 2    
(436)(437)     Summary     MMU Output KVA, Unit 2    
(438)(439)     Summary     MMU Input Power, Unit 2    
(440)(441)     Summary     MMU Input KVA, Unit 2    
(442)(443)     Summary     MMU Spare telemetry channel, Unit 2    
(444)(445)     Summary     MMU Spare telemetry channel, Unit 2    
(446)(447)     Summary     MMU Input Current Phase A, Unit 2    
(448)(449)     Summary     MMU Input Current Phase B, Unit 2    
(450)(451)     Summary     MMU Input Current Phase C, Unit 2    
(452)(453)(     Summary     MMU Output Current Phase A, Unit 2    
(454)(455)     Summary     MMU Output Current Phase B, Unit 2    
(456)(457)     Summary     MMU Output Current Phase C, Unit 2    
(468)     Summary     MMU Mode, Unit 3    
(469)     Summary     MMU State, Unit 3    
(470)(471)     Summary     Tachometer, Unit 3    
(472)(473)     Summary     Percent Usable Energy, Unit 3    
(474)(475)     Summary     Cabinet Temperature, Unit 3    
(476)(477)     Summary     Vacuum Gauge, Unit 3    
(478)(479)     Summary     MMU Output Power, Unit 3    
(480)(481)     Summary     MMU Output KVA, Unit 3    
(482)(483)     Summary     MMU Input Power, Unit 3    
(484)(485)     Summary     MMU Input KVA, Unit 3    
(486)(487)     Summary     MMU Spare telemetry channel, Unit 3    
(488)(489)     Summary     MMU Spare telemetry channel, Unit 3    
(490)(491)     Summary     MMU Input Current Phase A, Unit 3    
(492)(493)     Summary     MMU Input Current Phase B, Unit 3    
(494)(495)     Summary     MMU Input Current Phase C, Unit 3    
(496)(497)     Summary     MMU Output Current Phase A, Unit 3    
(498)(499)     Summary     MMU Output Current Phase B, Unit 3    
(500)(501)     Summary     MMU Output Current Phase C, Unit 3    
(512)     Summary     MMU Mode, Unit 4    
(513)     Summary     MMU State, Unit 4    
(514)(515)     Summary     Tachometer, Unit 4    
(516)(517)     Summary     Percent Usable Energy, Unit 4    
(518)(519)     Summary     Cabinet Temperature, Unit 4    
(520)(521)     Summary     Vacuum Gauge, Unit 4    
(522)(523)     Summary     MMU Output Power, Unit 4    
(524)(525)     Summary     MMU Output KVA, Unit 4    
(526)(527)     Summary     MMU Input Power, Unit 4    
(528)(529)     Summary     MMU Input KVA, Unit 4    
(530)(531)     Summary     MMU Spare telemetry channel, Unit 4    
(532)(533)     Summary     MMU Spare telemetry channel, Unit 4    
(534)(535)     Summary     MMU Input Current Phase A, Unit 4    
(536)(537)     Summary     MMU Input Current Phase B, Unit 4    
(538)(539)     Summary     MMU Input Current Phase C, Unit 4    
(540)(541)     Summary     MMU Output Current Phase A, Unit 4    
(542)(543)     Summary     MMU Output Current Phase B, Unit 4    
(544)(545)     Summary     MMU Output Current Phase C, Unit 4    
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